1. Field of the Invention
The invention relates generally to chip carrier substrates used within semiconductor fabrication. More particularly, the invention relates to chip carrier substrates fabricated with enhanced efficiency.
2. Description of the Related Art
In order to provide enhanced levels of connectivity, as well as increased power distribution and signal processing options, semiconductor chips are often mated and affixed to chip carrier substrates. Chip carrier substrates typically include additional conductor layers and separating dielectric layers beyond those included within a semiconductor chip. Thus, chip carrier substrates provide enhanced levels of connectivity of a semiconductor chip to a further assembled higher level electrical component.
While chip carrier substrates are thus essential in providing enhanced performance to microelectronic circuits, chip carrier substrates are nonetheless not entirely without problems. In particular, additional advancements and enhancements in chip carrier substrate performance are generally desirable.
Various chip carrier substrates, and methods for fabrication thereof, are known in the semiconductor fabrication art. In particular, Chudzik et al., in U.S. Pub. No. 2004/0108587, teaches a chip carrier substrate with enhanced capabilities. This particular chip carrier substrate includes a passive decoupling device, such as a decoupling capacitor or a decoupling resistor, in addition to the conventional conductor interconnect layers that are separated by dielectric layers within the chip carrier substrate.
Chip carrier substrates are likely to be of considerable continued interest in microelectronic fabrication since continued enhancements in performance and functionality of microelectronic circuits is desirable. Thus, also desirable are chip carrier substrates with enhanced performance, and methods for fabrication thereof.